I’ve mentioned this before on previous occasions, but it’s worth repeating to set the scene. When I graduated from Sheffield Hallam University with my BSc in Control engineering in 1980, my first job was as a member of a team creating central processing units (CPUs) for mainframe computers. This involved designing application-specific integrated circuits (ASICs) implemented at the 5-micron process / technology node.

Looking back, I find it amazing to think that we did all our design work at the gate- and register-level of abstraction using pencil and paper. No one I knew at that time could afford even a rudimentary four-function electronic calculator.

Things are getting complicated (Click image to see a larger version — Image source: Pixabay)

Functional verification involved the other members of the team looking at your schematics and asking probing questions like “What’s this bit do?” and “Why did you do it this way instead of that way?” Eventually, when they grudgingly said, “Well, it should work,” you could breathe a sigh of relief because you’d passed the first hurdle.

Timing verification tools? Don’t make me laugh. We identified critical paths based on experience and then added all the gate and wire delays by hand using our trusty pencils and paper again.

Performing layout versus schematic (LVS) involved printing the layout out on long strips of fanfold paper and sticking them together to form a square 20-feet to 30-feet on each side depending on the device. The layout was represented in ASCII, where ‘N’ and ‘P’ characters represented N-type and P-type silicon, respectively; ‘1’ and ‘2’ characters represented metallization layers 1 and 2, respectively; an ‘X’ character represented a via between metallization layers 1 and 2; and so forth. We then spent countless hours walking around the layout wearing clean pairs of socks (shoes would tear the paper and bare feet would stick to it) marking off things like gates and wires in both the schematics and the layout using colored pencils. I don’t like to boast, but we sharpened our pencils as we walked—that’s just the sort of rugged, no-nonsense engineers we were. The goal was to complete the process with everything colored in; the fear was that you’d end up with something uncolored in either the schematic or the layout.

Oh, how things have changed. Today’s systems are becoming ever-more sophisticated and complex, increasingly pushing the boundaries of what is possible, resulting in a hyperconvergence of design domains that demands multiphysics simulations. One exciting development is the emerging use of artificial intelligence (AI), machine learning (ML), and deep learning (DL) in both the design and verification arenas.

On the one hand, we are still in the very early days of deploying these technologies in design and verification space (where no one can hear you scream). On the other hand, the speed with which technologies and tools have changed in my own lifetime (“I’ve seen things you people wouldn’t believe”) has taught me to “expect the unexpected,” as it were. What I’m currently seeing leads me to believe that the world of electronic design—embracing chiplets, chips, modules, packages, boards, systems—is about to undergo a metamorphosis that will leave us gasping in awe. I for one can’t wait. I hope you’ll join me here as we explore this exciting and evolving space together.