When you saw the title of this blog, did your mind “throw a wobbly” for a moment and cause you to exclaim “Say what?”
I know, right?
The thing is that I just ran across a project on Hackaday.io for something called the Pineapple ONE, which was created by user filip.szkandera who describes himself as a student who likes to make home-brew central processing units (CPUs).
Filip’s goal was to build his own RISC-V CPU. As you may know, RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA). This instruction set is designed for a wide range of uses. It is variable-width and extensible so that more encoding bits can always be added. It supports three word-widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset vary slightly for the three word-widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale rack-mounted parallel computers.
The most basic RISC-V CPU that is supported by compilers must include the extension “I” (Integer) and its data bus must be at least 32 bits wide, so that’s what Filip set out to build.
I have to take my hat off to Filip. At the beginning of this project he determined to not use any microcontrollers or FPGAs in the build (thereby making his life much harder), just basic discrete logic integrated circuits, primarily of the 7400 series flavor. The details of his build make for a fascinating story.
As an aside, this just reminded me of my Magic Rings of Homegrown Computers blog. I don’t see the Pineapple ONE in the ring, so I’m going to suggest to Filip that he contacts the organizer to have it added ASAP.
So, what say you? Are you as impressed by this project as am I?
This reminds me of a class project when I was in college. We had to design a RISC computer using 7400 logic (SSI and MSI only). Fortunately for me, we only had to produce schematics and didn’t have to build it. Just getting the schematics done was a significant achievement for a one term class.
I expect that if we’d been required to build one it would have looked much like the on Filip made only not as neat and likely would have taken at least a year.
This was in the old days where the schematic drawings were done on paper with pencil and we didn’t have access to much in the way of simulations. These days the college class probably requires students to create the RISC computer in FPGA form.
My first job out of university was as a member of a team designing CPUs for mainframe computers. As you say, there were no simulators or timing analyzers or layout tools — -it was all done by hand — and all of the schematics were captured at the gate-level (e.g. AND, OR) and register-level (e.g. D-type flip-flop) using pencil and paper — ah, the good old days 🙂
See also: https://spectrum.ieee.org/geek-life/hands-on/build-a-riscv-cpu-from-scratch