Generally speaking, I like to feel that I keep abreast of technological developments — especially in my home territories of silicon chips and embedded systems — so it’s a big disconcerting to keep on being surprised by new developments that I didn’t even know were in the works.

Xilinx is now employing state-of-the-art lidless packing technology (Click image to see a larger version — Image source: Xilinx)

This happened to me just the other day when I was chatting with the chaps and chapesses at Xilinx about their most recent offerings in the form of their Versal Adaptive Compute Acceleration Platform (ACAP) devices, all of which are implemented at the 7 nm technology node.

As some point in our conversation, it dawned on me that — in much the same way that no one said anything in the presence of the emperor who wore no clothes — no one was mentioning the fact that the Versal chip package was wearing no lid.

When I casually dropped this tidbit of trivia into the conversation, everyone did their best to appear nonchalant, but I got the impression they were secretly rather proud that I’d noticed. It turns out that, as I discuss in this video, using lidless packages can offer amazing returns with regard to heat dissipation.


Following our call, the folks at Xilinx shared a slide with me showing four different thermal solutions involving lidded and lidless versions of one of their devices. This example reflects four different deployments of a 50-watt RFSoC device as often seen in wireless systems like Remote Radio Heads (RRHs).

Lidded versus lidless packaging example (Click image to see a larger version — Image source: Xilinx)

The first solution (left) is a traditional lidded device mounted in a traditional thermal design employing a traditional thermal pad to thermally connect the device to the external aluminum case.

The second solution is very similar, except that — instead of a lidded device — a lidless device is used with a floating lid that acts as a small heat spreader and gives a surface to allow for a more traditional thermal design; again, using a thermal pad.

The next solution incorporates an aluminum heat spreader thermally connected to the die and then thermally attached to the case via a thermal pad. The final solution (right) is similar to the prior incarnation, except that there is no heat spreader or thermal pad; instead, the die is in direct thermal contact with the case.

The results can be seen in the tables below the images. With the traditional lidded part in this configuration, near maximum junction temperature is achieved at room temperature, thereby disallowing operation at elevated ambient temperatures.

The second solution allows for a 15°C drop in maximum junction temperature by reducing the thermal resistance from the die through the floating lid to the thermal pad. The third solution incorporating the a larger heat spreader further drops the temperature to below maximum junction at 45°C ambient but with little margin. The final solution provides even more efficient heat dissipation, thereby allowing for 45°C ambient operation with a good thermal margin.

All I can say is that I, for one, am very impressed.

Returning to Versal ACAPs — these bodacious beauties are dynamically customizable at the hardware and software levels to fit a wide range of applications and workloads. All of this lead to another surprise (for me), which is that — while I wasn’t looking — the little scamps at Xilinx rearchitected their suite of design and verification tools (I tell you… you turn your back for a moment…).

Each type of user works with the tools at the most appropriate level of abstraction (Click image to see a larger version — Image source: Max Maxfield)

In the case of hardware developers, they will use Vivado Design Suite HLx Editions, which allows them to capture their designs in RTL using Verilog and/or VHDL and then simulate them and synthesize them using regular logic synthesis.

Alternatively, the hardware developers can move to a higher level of abstraction, capture and verify their designs in SystemC, and then use Vivado’s high-level synthesis (HDL) to process the design and generate the RTL that will be used to feed the regular synthesis.

Meanwhile, software developers will use the Vitis Unified Software Platform. The key point here is that each type of user only works with the tools at the most appropriate level of abstraction for what they understand and what they are trying to do. Thus, Vitis provides software developers with the ability to seamlessly build accelerated applications without being exposed to any of the nitty-gritty low-level hardware implementation details.

Similarly, Vitis AI allows artificial intelligence and data scientists to work at the TensorFlow level of abstraction without having to become embroiled in any of the nitty-gritty details that are relished by the software developers.

Now my head is spinning. Were you aware of all of these developments? If so, why didn’t you tell me?