I’ve said it before, and I’ll say it again – I know a lot of guys and gals who are heroes and heroines when it comes to using microcontrollers (MCUs) to create things like IoT edge devices and embedded systems, but who don’t have a clue how to design and deploy FPGAs. The thing is that many of these lads and lasses would desperately love to know more.

Happily, there’s going to be a free webinar on the topic of Getting Started with FPGAs on Thursday, 22 July at 9:00 a.m. PDT.

Hopefully I’ll see you at the webinar (Click image to see a larger version)

I’ll tell you more about this webinar in a moment, but first let’s set the scene and make sure we’re all tap-dancing to the same drumbeat. The term field-programmable gate array (FPGA) originated in the early 1980s, at which time the dominant form of application-specific integrated circuit (ASIC) was the gate array (GA). Any algorithms implemented in an ASIC are effectively “frozen in silicon,” so the “field-programmable” portion of the FPGA moniker was used to reflect the fact that the function of these devices could be determined in the field.

A key feature at the core of an FPGA is its programmable fabric. The way I like to visualize this is as large numbers of small “islands” of programmable logic sitting in a “sea” of programmable interconnect. Each island contains a number of logical elements like a look-up table (LUT), multiplexer, flip-flop, and so forth. Every aspect of these elements can be configured. In the case of a 4-input LUT, for example, this little scamp can be programmed to reflect any conceivable 4-input combinatorial logic function.

By programming the interconnect, we connect the outputs from each island to the inputs of other islands. We can also connect the inputs and outputs of selected islands to the FPGA’s primary general-purpose input/output (GPIO) pins. Speaking of the GPIOs, these can be programmed to present different impedances on the inputs, different slew rates on the outputs, and to support different electrical standards.

The ability to configure the programmable fabric means that we can persuade the FPGA to perform any function our hearts desire. We can even configure a portion of the fabric to act like one or more processor cores should we so wish. In this case, these would be called “soft cores” to reflect the fact that they were implemented using the FPGA’s programmable fabric. Many modern FPGA families also include “hard core” processors that are implemented directly in the silicon, along with other hard cores like high-speed serial communication functions.

One really big differentiator is the way in which in which MCUs and FPGAs implement data processing tasks. Ignoring things like multiple cores and multiple threads, an MCU executes its algorithms in a sequential manner, one instruction after another. As a result, while MCUs are wonderful when it comes to implementing decision-making tasks, they can be painfully inefficient when it comes to manipulating large quantities of data. By comparison, the FPGA’s programmable fabric can be configured to perform appropriate algorithms in a massively parallel fashion, thereby dramatically increasing performance.

In the case of someone using an MCU, the software design intent is captured as a source file using a programming language like C/C++, which is subsequently run through a compiler to generate the executable machine code. It’s important to realize that this machine code is just a file of 0s and 1s until it’s loaded into the MCU’s memory and executed.

Similarly, in the case of someone using an FPGA, the hardware design intent is captured using a hardware description language (HDL) like Verilog or VHDL. These languages have been created in such a way as to facilitate the user’s ability to capture the way in which multiple events in hardware can happen concurrently (at the same time). The source HDL is then run through an appropriate compiler called a logic synthesis engine, which outputs a configuration file. Once again, this is just a file of 0s and 1s until it’s loaded into the FPGA and used to configure the islands of logic and the sea of interconnect.

And so we return to the Getting Started with FPGAs webinar, which – as I mentioned earlier – will take place on Thursday, 22 July at 9:00 a.m. PDT. This will be a panel discussion with Eleena Ong from Lattice Semiconductor, Martin Kellermann from Microchip, and Jayson Bethurem from Xilinx, all hosted and moderated by Kevin Keryk from Avnet.

In addition to a cornucopia of other subjects, some key topics of conversation will be “What is the best way to begin developing with FPGAs?” and “What kinds of training resources are available for new users?” and “When should you select an FPGA instead of an ASIC, MPU, or GPU?”

So, over to you. If you are interested in learning more, I suggest that you bounce over to Register ASAP before all of the good virtual seats are taken. I’ve already registered myself because I like to keep my thumb on the pulse of what’s going on, so hopefully I’ll see you there.